CVE-2026-29643

XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.

CVSS v3 7.1 HIGH

7.1^/10

CVSS v3 : HIGH

Vector :

Exploitability : 1.8 / Impact : 5.2

Attack Vector LOCAL

Attack Complexity LOW

Privileges Required LOW

User Interaction NONE

Confidentiality Impact NONE

Integrity Impact HIGH

Availability Impact HIGH

Scope UNCHANGED

References

Link	Resource
https://docs.riscv.org/reference/isa/priv/machine.html
https://docs.riscv.org/reference/isa/priv/priv-csrs.html
https://github.com/OpenXiangShan/XiangShan/issues/3959
https://github.com/OpenXiangShan/XiangShan/pull/3966
https://github.com/OpenXiangShan/XiangShan/issues/3959

Configurations

No configuration.

History

No history.

Information

Published : 2026-04-20 22:16

Updated : 2026-06-17 10:29

NVD link : CVE-2026-29643

Mitre link : CVE-2026-29643

CVE.ORG link : CVE-2026-29643

JSON object : View

Products Affected

No product.

CWE

CWE-703

Improper Check or Handling of Exceptional Conditions

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