An issue has been identified in Arm C1-Pro before r1p2-50eac0, where, under certain conditions, a TLBI+DSB might fail to ensure the completion of memory accesses related to SME.
References
| Link | Resource |
|---|---|
| https://developer.arm.com/documentation/111823 | Vendor Advisory |
Configurations
Configuration 1 (hide)
| AND |
|
History
No history.
Information
Published : 2026-03-02 15:16
Updated : 2026-06-17 10:11
NVD link : CVE-2026-0995
Mitre link : CVE-2026-0995
CVE.ORG link : CVE-2026-0995
JSON object : View
Products Affected
arm
- c1-pro_firmware
- c1-pro
CWE
CWE-362
Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')
